1. Field of the Invention
The present invention relates to semiconductor device fabrication and more particularly, to a method of forming a trench isolation structure provided in a semiconductor device, which uses spin coating.
2. Description of the Prior Art
The isolation structure of a semiconductor device is, in general, provided to electrically isolate a semiconductor element or elements such as transistors, resistors, and capacitors in an active region from other semiconductor element or elements in a neighboring active region on a same semiconductor substrate.
In recent years, the need to narrow the isolation regions has been becoming stronger with the increasing level of integration of Large-Scale Integrated circuits (LSIs). Thus, with the well-known LOcal Oxidation of Silicon (LOCOS) method where the isolation regions are formed by producing a patterned isolation dielectric on a main surface of a semiconductor substrate of silicon (Si) due to selective oxidation, the isolation regions corresponding to a desired integration level have been being unable to be realized.
To respond to the need, the "trench isolation structures" has been often used, in which neighboring active regions are electrically isolated from one another by an isolation dielectric filled in trenches formed vertically into a semiconductor substrate. The isolation dielectric is typically made of silicon dioxide (SiO.sub.2). The trenches are formed in the substrate according to a desired pattern of isolation regions and then, the isolation dielectric is selectively formed so as to fill the trenches.
The trench isolation structure makes it possible to decrease the width of the isolation trenches (i.e., the isolation regions) compared with the isolation regions realized by the conventional LOCOS method. Thus, the trench isolation structure can produce narrower isolation regions corresponding to a recent, high integration level of LSIs.
A conventional method of forming the trench isolation structure is explained below with reference to FIGS. 1A to 1E. In this method, it is needless to say that a lot of isolation trenches are formed in a semiconductor substrate to electrically isolate adjoining active regions from one another. However, only one of the trenches is illustrated to isolate two adjoining ones of the active regions and explained below for the sake of simplification of description.
It is known that Chemical Vapor Deposition (CVD) is effective to form selectively an isolation dielectric of SiO.sub.2 to fill fine isolation trenches (e.g., approximately 0.1 .mu.m in width), because CVD produces SiO.sub.2 with a good filling property of the trenches, in other words, SiO.sub.2 produced by CVD (i.e., CVD-SiO.sub.2) has a good trench-filling property. In the conventional method explained below with reference to FIGS. 1A to 1E, high-density plasma CVD, which produces SiO.sub.2 with a better trench-filling property, is used.
First, a SiO.sub.2 film 105 with a thickness of approximately 20 nm, which serves as a pad oxide, is formed on a main surface of a single-crystal Si substrate 101 by thermal oxidation of the substrate 101. Then, a silicon nitride (Si.sub.3 N.sub.4) film 106 with a thickness of approximately 200 nm is formed on the SiO.sub.2 film 105 by reduced-pressure CVD. The Si.sub.3 N.sub.4 film 106 is used as a mask for an isolation trench. The state at this stage is shown in FIG. 1A.
Next, after a photoresist film (not shown) is formed on the Si.sub.3 N.sub.4 film 106 by coating, the photoresist film is patterned by popular exposure and development processes. The patterned photoresist film has a pattern corresponding to the plan shape of a desired isolation trench. In other words, the photoresist film has a window corresponding to the isolation trench to be formed.
Using the patterned photoresist film as a mask, the Si.sub.3 N.sub.4 film 106 and the SiO.sub.2 film 105 are successively patterned by dry etching. Thus, a hole 118 is formed to penetrate through the Si.sub.3 N.sub.4 and SiO.sub.2 films 106 and 105. The hole 118, which has a plan shape corresponding to the window of the photoresist film, is reached the main surface of the substrate 101, as shown in FIG. 1B.
After removing the photoresist film, the main surface of the substrate 101 is selectively and vertically removed by dry etching using the Si.sub.3 N.sub.4 film 106 as a mask, thereby forming an isolation trench 103 in the substrate 101, as shown in FIG. 1C. The isolation trench 103 has a plan shape corresponding to the window of the photoresist film. For example, the trench 103 has a width of 0.1 .mu.m and a depth of 0.5 .mu.m, resulting in an aspect ratio of 5 (=0.5/0.1).
Subsequently, as shown in FIG. 1D, a SiO.sub.2 film 113 is formed on the Si.sub.3 N.sub.4 film 106 to cover the whole main surface of the substrate 101. The formation process of the SiO.sub.2 film 113 is carried out by high-density plasma CVD that produces SiO.sub.2 with a better trench-filling property. As a result, the SiO.sub.2 film 113 is deposited on the Si.sub.3 N.sub.4 film 106 and at the same time, it is deposited in the trench 103 and the penetrating hole 118. The state at this stage is shown in FIG. 1D.
The SiO.sub.2 film 113 is then polished by Chemical Mechanical Polishing (CMP) until the surface of the underlying Si.sub.3 N.sub.4 film 106 is exposed. Thus, the SiO.sub.2 film 113 is removed while the part of the SiO.sub.2 film 113 located under the surface of the Si.sub.3 N.sub.4 film 106 is left and at the same time, the surface of the Si.sub.3 N.sub.4 film 106 is planarized.
Finally, the remaining Si.sub.3 N.sub.4 film 106 and the underlying SiO.sub.2 film 105 are successively removed by wet etching. As a result, as shown in FIG. 1E, only the part of the SiO.sub.2 film 113 located under the surface of the Si.sub.3 N.sub.4 film 106 is left. The remaining part of the SiO.sub.2 film 113, almost all of which is located in the trench 103 and a top of which is protruded from the main surface of the substrate 101 by a height corresponding to the total thickness of the films 106 and 105, serves as an isolation dielectric. The trench 103 and the remaining SiO.sub.2 film 113 constitute a trench isolation structure 102 that isolates electrically two adjoining active regions A101 and A102.
With the conventional method of forming a trench isolation structure shown in FIGS. 1A to 1E, a void (i.e., unfilled part) 114 tends to be formed in the remaining SiO.sub.2 film 113 (i.e., the isolation dielectric) during the process of forming the SiO.sub.2 film 113 by high-density plasma CVD, as shown in FIG. 1D. This is caused by the fact that the isolation trench 103 is narrow in width and high in aspect ratio. In this case, even if high-density plasma CVD, which produces SiO.sub.2 with a better trench-filling property, is used for forming the SiO.sub.2 film 113, the whole trench 103 is difficult to be filled with the SiO.sub.2 film 113.
If the void 114 exists in the isolation dielectric 113, not only the mechanical strength of the trench isolation structure 102 but also the electrical isolation capability thereof will degrade. Also, there is a possibility that the void 114 appears on the main surface of the substrate 101 after the CMP process of the SiO.sub.2 film 113, as shown in FIG. 1E in this case, the exposed void 114 will cause a problem that overlying wiring layers or lines (which will be formed in subsequent processes) are broken or cut.
As an improvement of the above-described conventional method shown in FIGS. 1A to 1E, a method using a different condition of the high-density plasma CVD has been developed. In this method, the void 114 is prevented from being generated due to the enhanced plasma-etching action.
With the improved method using the different CVD condition, although the void 114 can be prevented, the neighborhood of the hole 118 of the films 106 and 105 and the top of the isolation trench 103 tend to be etched by the enhanced plasma-etching action. As a result, as shown in FIG. 2, the sidewalls of the hole 118 and the trench 103 become oblique. The oblique sidewalls 115 of the trench 103 and the hole 118 lead to substantial expansion of the trench 103 or isolation regions with respect to that of the conventional method of FIGS. 1A to 1E, which is contrary to the need to shrink the isolation regions. Moreover, the expanded trench 103 will cause a problem that current leakage is increased due to degraded isolation capability.
On the other hand, it has been known that so-called "spin coating" is effective to produce SiO.sub.2 with a good trench-filling property. The spin coating process may be termed the "Spin-On-Glass (SOG)" process. When this spin coating or SOG process is used, a solution of a Si-containing material is dropped onto a main surface of a Si substrate (or, a layer located on the substrate) while rotating the substrate in a horizontal plane, thereby forming a uniformly-coated film of the solution on the entire main surface of the substrate (or, the layer located on the substrate) due to the effect of centrifugal force. Subsequently, the substrate 101 is heated to vaporize or volatilize the solvent of the solution from the coated film and to cause a chemical reaction of the Si-containing material with oxygen existing in the atmosphere, thereby forming a SiO.sub.2 film on the whole main surface of the substrate 101 (or, the layer located on the substrate).
With the method using the spin coating process, since the solution of the Si-containing material is dropped onto the surface of the substrate (or, the layer located on the substrate) and coated thereon by the effect of centrifugal force, there arises an advantage of excellent trench-filling property. As the solution of the Si-containing material, a solution containing silicon hydroxide (i.e., silanol, SiOH.sub.4) dispersed in an organic solvent such as alcohol is typically used.
A conventional method of forming a trench isolation structure using the above-described spin coating or SOG process is shown in FIGS. 3A and 3B.
First, in the same way as shown in the above-described conventional method of FIGS. 1A to 1E, an isolation trench 103 is formed in a Si substrate 101 with a SiO.sub.2 film 105 and a Si.sub.3 N.sub.4 film 106, as shown in FIG. 3A. Then, through a spin coating process using a solution containing SiOH.sub.4 dispersed in an organic solvent, a film 107 of the SiOH.sub.4 solution is formed on the Si.sub.3 N.sub.4 film 106 to cover the whole main surface of the substrate 101. At this stage, the film 107 fills the entire trench 103 and the entire hole 118, as shown in FIG. 3A.
Subsequently, the film 107 of the SiOH.sub.4 solution is subjected to a specified heat treatment, thereby converting the film 107 to a SiO.sub.2 film 104 due to hydrolysis and dehydrating condensation reactions.
Finally, in the same way as shown in the above-described conventional method of FIGS. 1A to 1E, the SiO.sub.2 film 104 located over the surface of the Si.sub.3 N.sub.4 film 106 is selectively removed by CMP and then, the Si.sub.3 N.sub.4 film 106 and the SiO.sub.2 film 105 are successively removed by wet etching. As a result, the part of the SiO.sub.2 film 104 located below the surface of the Si.sub.3 N.sub.4 film 106 is left in the trench 103 and the hole 118, thereby forming a trench isolation structure 102 that isolates electrically two adjoining active regions A101 and A102, as shown in FIG. 33.
The conventional method using the spin coating shown in FIGS. 3A and 3B, however, has the following problem.
During the heat-treatment process for converting the Si-containing material film 107 to the SiO.sub.2 film 104, a large-volume shrinkage occurs in the film 107 due to the dehydrating condensation reaction. As a result, the part of the SiO.sub.2 film 104 located in the trench 103 and the hole 118 (i.e., the isolation dielectric), which has a comparatively larger thickness or height than the remaining part, is unable to resist the shrinkage action, resulting in cracks 117 in the remaining SiO.sub.2 film 104, as shown in FIG. 3B.
Furthermore, it has been known that the SiO.sub.2 film 104 generated by the dehydrating condensation reaction of SiOH.sub.4 contains a lot of SiOH.sub.4 groups as well as the film 104 is porous due to insufficient densification. These properties of she SiO.sub.2 film 104 affect badly the CMP process for removing selectively the SiO.sub.2 film 104 and/or the wet etching processes for removing the Si.sub.3 N.sub.4 film 106 and the SiO.sub.2 film 105. As a result, the top of the remaining SiO.sub.2 film 104 tends to be lowered to form a depression or hollow 116 thereon in the trench 103, as shown in FIG. 3B.
In particular, when the pad SiO.sub.2 film 105 is formed by thermal oxidation, the depression or hollow 116 is likely to be formed. This is due to the fact that the SiO.sub.2 film 104 generated by the chemical reaction of the film 107 of the SiOH.sub.4 solution is much larger in etch rate than the SiO.sub.2 film 105 formed by thermal oxidation in the wet etching process for removing the SiO.sub.2 film 105.
As described above, the conventional method shown in FIGS. 1A to 1E has a problem that the void 106 tends to be formed in the remaining SiO.sub.2 film 113 in the isolation trench 103. The conventional method shown in FIG. 2 solves this problem relating to the void 106. However, it has a problem that the isolation region is expanded, the isolation capability is degraded, and the current leakage is increased. The conventional method shown in FIGS. 3A and 3B has a problem that the cracks 117 and/or the depression 116 tend to be formed in the remaining SiO.sub.2 film 104 in the isolation trench 103.